The present invention relates generally to the mounting of semiconductor devices on a substrate or circuit board. The invention relates in particular with regards to the fabrication of raster input scanner arrays. The invention relates most particularly to the mounting of silicon image sensor chips/dies so as to achieve a collinear Full Width image sensor Array (FWA).
Image sensor dies for scanning document images, such as Charge Coupled Devices (CCDs), typically have a row or linear array of photo-sites together with suitable supporting circuitry integrated onto silicon. Usually, a die of this type is used to scan line by line across the width of a document with the document being moved or stepped lengthwise in synchronism therewith. In the alternative, the image sensor can be moved lengthwise with the document in a stationary position.
In the above application, the image resolution is proportional to the ratio of the scan width and the number of array photo-sites. Because of the difficulty in economically designing and fabricating long dies, image resolution for the typical die commercially available today is relatively low when the die is used to scan a full line. While resolution may be improved electronically as by interpolating extra image signals, or by interlacing several smaller dies with one another in a non-collinear fashion so as to crossover from one die to the next as scanning along the line progresses, electronic manipulations of this type adds to both the complexity and the cost of the system. Further, single or multiple die combinations such as described above usually require more complex and expensive optical systems.
However, a long or full width array, having a length equal to or larger than the document line and with a large packing of colinear photo-sites to assure high resolution, has been and remains a very desirable arrangement. In the pursuit of a long or full width array, forming the array by assembling several small dies together end to end has become an exemplary arrangement. However, this necessitates providing dies whose photo-sites extend to the border or edge of the die, so as to assure photo-site continuity when the die is assembled abutted end to end with other dies. By the same token when that is achieved it follows that the chip dies must be mounted in such a manner so as to assure close proximity of the photo-sites of one chip with the photo-sites of an abutting chip die. FWA""s assembled with dies that are mounted with excessive gap between them suffer from image quality degradation due to lost image information at the gap locations.
One essential parameter in the fabrication of a FWA for which allowances must be made in any attempt at maintaining gap tolerances, is the thermal coefficient of the chip/dies relative to any substrate that the chip/dies are ultimately mounted upon. The prior approach has been to use a mounting substrate with a thermal coefficient that matches the thermal coefficient of the silicon chips. In particular, one printed circuit board (PCB) substrate of a specialty type typically used Ceracom, has a thermal coefficient of expansion (TCE) of six parts per million per degree centigrade (TCE=6 PPM/xc2x0 C.). This compares favorably with a silicon TCE=3 PPM/xc2x0 C. for the chip/dies.
However, Ceracom is expensive, and it would be very desirable to use a more cost effective solution as a substrate. In particular, it would be desirable, for example, to use an industry standard material such as FR-4. Unfortunately, FR-4 has a TCE of 13 PPM/xc2x0 C.
Therefore, as discussed above, there exists a need for an arrangement and methodology which will solve the problem of preventing large gaps between chips mounted upon a substrate while allowing a cost effective material for the substrate. Thus, it would be desirable to solve this and other deficiencies and disadvantages as discussed above with an improved methodology for mounting, bonding, and curing chips upon a substrate while minimizing chip-to-chip gap.
The present invention relates to a method for assembling chips upon a substrate comprising arcing a curve in the substrate by applying restraining forces and placing the chips upon the curved substrate with an initial gap between the chips. This is followed by allowing a thermal cycle and releasing the restraining forces to allow the substrate to return to stasis.
The present invention also relates to a method for assembling chips upon a substrate comprising arcing a convex curve in the substrate by applying restraining forces, placing the chips upon the curved substrate with an initial gap between the chips, and releasing the restraining forces to allow the substrate to return to stasis.
The present invention further relates to a method for assembling chips upon a substrate comprising placing one face of the substrate against a convex restraining plate and applying restraining forces to the opposite face of the substrate to establish an arc in the substrate. This is followed by placing the chips upon the curved substrate with an initial gap between the chips, allowing a thermal cycle, and releasing the restraining forces to allow the substrate to return to stasis.
The present invention also relates to a method for assembling chips upon a substrate to make a full width array comprising choosing a radius of curvature and applying that radius of curvature to a first face of a convex restraining plate, then placing one face of the substrate against the first face of the convex restraining plate and applying restraining forces to the opposite face of the substrate to establish an arc in the substrate. This is followed by placing the chips with adhesive upon the curved substrate with an initial gap between the chips, allowing a thermal cycle of the curing adhesive, and releasing the restraining forces to allow the substrate to return to stasis.
The present invention further relates to a method for assembling chips upon a substrate comprising arcing a first curve in the substrate by applying restraining forces and placing the chips upon the curved substrate with an initial gap between the chips. Then arcing a second curve in the substrate by applying restraining forces, allowing a thermal cycle, and releasing the restraining forces to allow the substrate to return to stasis.